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www.siliconstandard.com 1 of 14 ss6341 high performa nce, triple - output, auto - tracking co m bo controller n features l provides three accurately regulated output voltages l optimized voltage - mode pwm control l dual n - channel mosfet synchronous drivers l fast transient response l adjustable over - current protection using external mosfet r ds( on ) - no external current sense resistors required. l programmable soft start function l 200khz free - running oscillator l r obust output auto - tracking characteristics l sink and source capabilities with external circuit n applications l advanced pc motherboards l information pc s l servers and workstations l i nternet a ppliances l lcd monitor l pc add - on cards l ddr termination n general descr iption the ss6341 combines a synchronous voltage - mode pwm controller with two linear controller s , including the associated monitoring and protection functions. it is able to power cpu s , gpus, memories, chipset s and multi - voltage applications. the pwm controller regulates the output voltage using a synchronous rectified step - down converter. the built - in n - channel mosfet driver s also help to simplify the design of the step - down converter. the pwm controller features over - current protection using the r ds ( on ) of the external mosfet, improving efficiency and cost, as there is no expensive current sense resistor required. two built - in adjustable linear controllers drive external mosfets to form two linear regulators that regulate power for multiple system i /os. the o utput voltage of both linear regulators can also be adjusted by means of an external resistor divider. both linear regulators feature current - limiting. for system i/os requiring current less than 500ma, the ss6340 is recommended as it saves one exte r nal mosfet. the programmable soft - start design prov i des a controlled output voltage rise, which limits the current during power - on. a shutdown function is also provided , for disabl ing the combo controller . re v . 2.01 6/26/2003
www.siliconstandard.com 2 of 14 ss6341 n typical application circuit + + ugate phase vin 2 lgate gate3 pgnd fb3 gate2 fb2 comp1 ss gnd +5vin vcc +12vin 15 ocset 4 7 11 8 6 vout2 vout3 +3.3vin 12 13 16 1 2 14 14 vout1 + 5 gnd fb1 3 sd 10 + +3.3vin ss6341cs q1 q2 typical application with three outputs n ordering information pin configuration so -16 top view packing type tr: tape & reel tb: tube packaging type s: small outline 1 3 4 2 5 7 6 8 fb2 ugate sd vcc phase ss vin2 gate2 ocset lgate pgnd fb3 fb1 comp1 gate3 gnd 16 14 15 13 12 11 9 10 ss6341cxxx example: SS6341CSTR in so-16 package shipped in tape & reel packing re v . 2.01 6/26/2003
www.siliconstandard.com 3 of 14 ss6341 n absolute maximum rating s supply voltage (vcc) .................................................................................................................. 15v ugate ...................................................................................................... gnd - 0.3v to v cc + 0.3v lgate ....................................................................................................... gnd - 0.3v to v cc + 0.3v input output and i/o voltage ...................................................................................g nd - 0.3v to 7v recommended operating conditions ambient temperature range .......................................................................................... 0 c to 85 c maximum operating junction temperature .............................................................................. 100 c supply voltage, vcc .......................................................................................................... 15 v 10% thermal information thermal resistance q ja ( c/w) soic package ........................................................................................................... 100 c /w maximum juncti on temperature (plastic package) .................................................................. 150 c maximum storage temperature range ...................................................................... - 65 c to 150 c maximum lead temperature (soldering 10s) ........................................................................... 300 c n test circuit refer to the application circuit on page 14. n electrical characteristics (v cc =12v, t j =25 c , unless other wise specified) parameter test conditions symbol min. typ. max. unit vcc supply current supply current ugate, lgate, gate2 and gate3 open i cc 1.8 5 ma power on reset rising vcc threshold v ocset =4.5v vcc thr 8.6 9.5 10.4 v falling vcc threshold v o cset =4.5v vcc thf 8.2 9.2 10.2 v rising vin2 under - voltage threshold vin2 thr 2.5 2.6 2.7 v vin2 under - voltage hysteresis vin2 hys 130 mv rising v ocset1 threshold v ocseth 1.3 v re v . 2.01 6/26/2003
www.siliconstandard.com 4 of 14 ss6341 n electrical characteristics (continued) parameter test condition s symbol min. typ. max. unit oscillator and reference free running frequency f 170 200 230 khz fb 1 reference voltage v ref 1 1.287 1.300 1.313 v fb2 reference voltage v ref2 1.245 1.270 1.295 v fb3 reference voltage v ref3 1.250 1.275 1.300 v li near controller regulation 0 < i gate2/3 < 10ma - 2.5 +2.5 % under - voltage level fb2/3 falling fb2/3 uv 70 80 % pwm controller error amplifier dc gain 76 db gain bandwidth product gbwp 11 mhz slew rate comp1=10pf sr 6 v/ m s pwm controller ga te driver upper drive source vcc=12v, v ugate =11v r ugh 5.2 6.5 w upper drive sink vcc=12v, v ugate =1v r ugl 3.3 5 w lower drive source vcc=12v, v lgate =11v r lgh 4.1 6 w lower drive sink vcc=12v, v lgate =1v r lgl 3 5 w protection soft - start current i ss 11 m a chip shutdown soft start threshold 1.0 v re v . 2.01 6/26/2003
www.siliconstandard.com 5 of 14 ss6341 n pin descriptions pin 1: phase: over - current detection pin. connect to the source of the external high - side n - mosfet. this pin detects the voltage drop across the high - side n - mosfet r ds(on) for o ver - current protection. pin 2: ugate: external high - side n - mosfet gate drive pin. connect to the gate of the external high - side n - mosfet. pin 3: sd: to shut down the system, active high or floating. if connecting a resistor to ground, keep the resistor les s than 4.7k w . pin 4: vcc: the chip power supply pin. it also provides the gate bias charge for all the mosfets controlled by the ic. recommended supply voltage is 12v. pin 5: ss: soft - start pin. connect a capacitor from this pin to ground. this capacitor, along with an internal 10 m a (typically) current source, sets the soft - start interval of the converter. pulling this pin low will shut down the ic. pin 6: fb2: connect this pin to a resistor divider to set the linear regulator ou t put voltage. pin 7: vin2: connect this pin to a suitable 3.3v source. additionally, this pin is used to monitor the 3.3v supply. if the voltage drops below 2.6v (typically) following a start - up cycle, the chip shuts down. a new soft - start cycle is initiated upon the return of the 3.3v supply above the under - voltage threshold. pin 8: gate2: linear controller output drive pin. this pin can drive either a darlington npn transistor or an n - channel mosfet. pin 9: gnd: signal gnd for ic. all voltage levels are measured with respect to th is pin. pin 10: gate3: linear controller output drive pin. this pin can drive either a darlington npn transistor or an n - channel mosfet. pin 11: fb3 negative feedback pin for the linear controller error amplifier. connect this pin to a resistor divider to set the linear controller output voltage. pin 12: comp1 external compensation pin. connect to the error amplifier output and pwm comparator. an rc network is connected to fb1 to compensate the voltage control feedback loop of the co n verter. pin 13: fb1 the error amplifier inverting input pin. the fb1 pin and comp1 pin are used to compensate the voltage - control feedback loop. pin 14: ocset : current limit sense pin. connect a resistor r ocset from this pin to the drain of the external high - side n - mosfet. r ocse t , an internal 200 m a current source (i ocset ), and the upper n - mosfet on - resistance (r ds(on) ) set the over - current trip point according to the following equation: i i r r peak ocset ocset ds(on) = pin 15 : pgnd: driver power gnd pin. connect to a low impedance ground plane close to the lower n - mosfet source. pin 16 : lgate: lower n - mosfet gate drive pin. re v . 2.01 6/26/2003
www.siliconstandard.com 6 of 14 ss6341 n typical performance characteristics u gate l gate u gate l gate fig.1 the gate drive waveforms ss v out1 =3.15v v out1 =2.20v v out1 =1.30v ch1 2v/div ch2 1v/div fault ss 10a/div inductor current over load applied fig. 2 soft start initiates pwm output fig. 3 over - current operation on inductor re v . 2.01 6/26/2003
w w w .si l i c on st an d a r d . c om 7 of 14 ss6341 n typical performance characteristics (continued) 0 to 400ma load step v out2 v out1 5a to 12a load step 2.0v dc fig. 4 transient response of linear regulator fig. 5 transient response of pwm output v out3 ( 2mv/div ) 1a to 2a load step -20 0 20 40 60 80 1 00 180 185 190 195 200 205 210 ocset current ( m a) fig. 6 transient response of linear controller fig. 7 ocset current vs.temperature ( c ) -20 -10 0 10 20 30 40 50 60 70 80 90 100 9.25 9.30 9.35 9.40 9.45 9.50 9.55 ss charge current ( ua) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -0.2 -0.1 0.0 0.1 0.2 0.3 no load v out1 drift (mv) fig. 8 ss current vs. temperature ( c ) fig. 9 v out1 drift vs. vin (v) re v . 2.01 6/26/2003
www.siliconstandard.com 8 of 14 ss6341 n block diagram + + + + + + + + + + ssss por 5v - + 3.6v q r s q r s - + 0.2v 5v sd por 2.6v count 3 vin2 vcc 1.3v 200ua 9.5v fb2 gate2 ocset comp1 r r q s 1.3v fb3 oscillator gate control ss slow discharge fast discharge 20ua 10ua error amp pwm comp 200khz 70k 4v ss inhibit luv oc1 luv oc1 phase ugate vcc pgnd lgate vcc 0.3v 1.26v fb1 gate3 gnd n applications information the ss6341 is designed for applications with multiple voltage demand . this ic has one pwm controller and two linear controllers. the pwm controll er is designed to regulate the v oltage (v out1 ) by driving 2 mosfets ( through u gate and l gate ) in a synchronous rectified buck converter configuration. the regulated voltage level is decided by a resistor divider network . the power - on reset (por) function c ontinually monitors the +12v input supply voltage at vcc pin, the 5v input voltage at ocset pin, and the 3.3v input at vin2 pin. the por function initiates soft - start operation after all three input supply voltage exceed their por thresholds. soft - start th e por function initiates the soft - start sequence. initially, the voltage on the ss pin rapidly increases to approximate 1v. then an internal 10 a current source charges an external capacitor (c ss ) on the ss pin to 4v. as the ss pin voltage slews from 1v to 4v, the pwm error amplifier reference input (non - inverting terminal) and output (comp1 pin) are clamped to a level proportional to the ss pin voltage. as the ss pin voltage slews from 1v to 4v, the output clamp generates phase pulses of increasing width t hat charge the output capacitors. additionally both linear regulators? reference inputs are clamped to a voltage proportional to the ss pin voltage. this method provides a controlled smooth rise in output voltage. fig. 2 show s the soft - start sequence for a typical application. the internal oscillator?s triangular waveform is compared to the clamped error amplifier output voltage. as the ss pin voltage increases, the pulse width on the phase pin increases. the period of increasing pulse re v . 2.01 6/26/2003
www.siliconstandard.com 9 of 14 ss6341 width continues until the output reaches sufficient voltage to transfer control to the input reference clamp. each linear output (v out2 and v out3 ) initially follows a ramp. when each output reaches sufficient voltage, the input reference clamp slows the rate of output voltage rise. over - current protection all outputs are pr o tected against excessive over - current. the pwm controller uses the upper mosfet?s on - resistance, r ds(on) to monitor the current for protection against shorted outputs. both the linear regulator and controlle r monitor fb2 and fb3 for under - voltage to protect against excessive cu r rent. when the voltage across q1 (i d x r ds(on) ) exceeds the level (200 m a x r ocset ), this signal inhibits all outputs, discharges the soft - start capacitor (c ss ) with 10 m a current sink, and increments the counter. css recharges and initiates a soft - start cycle again until the counter increments to 3. this sets the fault latch to disable all outputs. fig. 3 illustrates the over - current protection for an over load on out1. should excessive current cause fb2 or fb3 to fall below the linear under - voltage threshold, the luv signal sets the over - current latch if css is fully charged. cycling the bias input power off then on resets the counter and the fault latch. the over - current function for t he pwm controller will trip at a peak inductor current (i peak ) determined by: i i r r peak ocset ocset ds(on) = the oc trip point varies with the mosfet?s temperature. to avoid over - current tripping in the normal operating load range, determine the r ocset resi s tor f rom the equation above with: 1. the maximum r ds(on) at the highest junction. 2. the minimum i ocset from the specification table. 3. ensure i peak > i out(max) + (inductor ripple current) /2. shutdown compatible with ttl logic levels, h olding the s d (pin3) p in low will activate the controller . if connecting a resistor to ground, make sure the resistor is less than 4.7k w for normal o p eration. layout consider a tions any inductance in the switched current path generates a large voltage spike during the switching interval. the voltage spikes can degrade efficiency, rad i ate noise into the circuit, and lead to device over - voltage stress. careful component selection and tight layout of critical components using short, wide metal traces minimizes these voltage spikes. 1) a ground plane should be used. locate the input capacitors (c in ) close to the power switches. minimize the loop formed by c in , the upper mosfet (q1) and the lower mosfet (q2) as much as possible. connections should be as wide and as short as possible to mi nimize loop inductance. 2) the connection between q1, q2 and output inductor should be as wide and as short as practical, as this connection has fast voltage transitions and can easily i n duce emi. 3) the output capacitor (c out ) should be located as close to the load as possible. minimizing the transient load magnitude for high slew rate requires low inductance and resistance in the circuit board. 4) the ss6341 is best placed over a quiet ground plane area. the gnd pin should be connected to the groundside of the output capacitors. under no circumstances should gnd be returned to a ground inside the c in , q1, and q2 loop. the gnd and pgnd pins should be shorted right at the ic. this helps to minimize internal ground disturbances in the ic and prevents differences in ground potential from disrupting the internal circuit operation. 5) the wiring traces from the control ic to the mosfet gate and source should be sized to carry a current of 1a. locate c out2 close to the ss6341. 6) the vcc pin should be decoupled directly to gnd by a 1 m f ceramic capacitor; trace lengths should be as short as possible. re v . 2.01 6/26/2003
www.siliconstandard.com 10 of 14 ss6341 a multi - layer printed circuit board is recommended. figure 10 shows the connections of the critical components in the converter. the c in and c out could each represent numerous p hysical capacitors. dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. pwm output capacitors the load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demand. the esr (equivalent series resistance) and esl (equivalent series inductance) parameters determine the buck capacitor values, rather than actual capacitance. for a given transient load magnitude, the output voltage t ransient change due to the output capac i tor can be found from the following equation: d d d d v esr i esl i t out out out = + where d i out is the transient load current step. + + + v out c out q1 +3.3v in +5v in l out gate3 c in q2 css ss gate2 pgnd lgate phase ugate ocset vin2 gnd vcc +12v + + q3 v out3 c out3 power plane layer circuit plane layer via connection to ground plane + q4 v out2 c out2 fig. 10 printed circuit board power planes and i slands re v . 2.01 6/26/2003
www.siliconstandard.com 11 of 14 ss6341 after the initial transient, the esl dependent term drops off. because of the strong relationship between output capacitor esr and output load transient, the output capacitor is usually chosen for esr, not for capacitance value. a capacitor with suitable esr will usually have a larger capacitance value than is needed for energy storage. a common way to lower esr and raise ripple current capability is to parallel several capacitors. in most case, multiple electrolytic capacitors of small case size are better than a single large case c a pacitor. output inductor selection the inductor value and type should be chosen based on output slew rate requirement, output ripple requirement and expected peak current, and is primarily controlled by the required c urrent response time. the ss6341 will provide either 0% or 85 % duty cycle in response to a load transient. the response time to a transient is different for the application of load and remove of load. t l i v v rise out in out = - d , t = l i v fall out out d where d i out is transient load current step. in a typical 5v input, 2v output application, a 3 m h inductor has a 1a/ m s rise time, resulting in a 5 m s delay in responding to a 5a load current step. to optimize performance, different comb inations of input and output voltage and expected loads may require different inductor values. a smaller value of inductor will improve the transient response at the expense of increased output ripple voltage and inductor core satur a tion rating. peak curr ent in the inductor will be equal to the maximum output load current plus half of inductor ripple current. the ripple current is approximately equal to: i = (v v ) v l v ripple in out out in - f where f = 200khz oscillator frequency. the inductor must be able to withstand p eak current without saturation, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss input capacitor selection most of the input supply current is supplied by the input bypass capacitor, and the result ing rms current flow in the input capacitor will heat it up. use a mix of input bulk capacitors to control the voltage overshoot across the upper mosfet. the ceramic capacitance for the high frequency decoupling should be placed very close to the upper mos fet to suppress the voltage induced in the parasitic circuit impedance. the buck capacitors to supply the rms current are approximate equal to: i (1 d) d i 1 12 v d f l rms 2 out in 2 = - + ? ? ? ? where d v v out in = the capacitor voltage rating should be at least 1.25 time s greater than the maximum input voltage. pwm mosfet selection in high current pwm application, the mosfet power dissipation, package type and heatsink are the dominant design factors. the conduction loss is the only component of power dissipation for the lower mosfet, since it turns on into near zero voltage. the upper mosfet has conduction loss and switching loss. the gate charge losses are proportional to the switching frequency and are dissipated by the ss6341. however, the gate charge increases the switching interval, t sw , which increase the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specif ications. p i r d i v t f 2 upper out 2 ds(on) out in sw = + p i r d) lower out 2 ds(on) = - ( 1 the equations above do not model the power loss from the reverse recovery of the lower mosfet?s body diode. the r ds(on) is different for the two previous equations re v . 2.01 6/26/2003
www.siliconstandard.com 12 of 14 ss6341 even if the same device type is us ed for both. this is because the gate drive applied to the upper mosfet is different than the lower mosfet. logic level mosfets should be selected based on on - resistance considerations. r ds(on) should be chosen based on input and output voltage, allowable power dissipation and maximum required output current. power dissipation should be calculated based primarily on required efficiency or allowable thermal dissip a tion. a schottky diode is used as a clamp to prevent the parasitic mosfet body diode from condu cting during the dead time between the turn off of the lower mosfet and the turn on of the upper mosfet. the diode?s rated reverse breakdown voltage must be greater than twice the maximum input voltage. linear controller mosfet selection the power dissipat ed in a linear regulator is : ) v (v i p out in2 out linear -= select a package and heatsink that maintains junction temperature below the maximum rating while operating at the highest expected ambient temperature. linear output capacitor the output capacitors for the linear controller provide dynamic load current. the linear controller uses dominant pole compensation integrated in the error amplifier and is insensitive to output capacitor selection. c out2 and c out3 should be selected for transient load regulation. notes v out1 - the pwm output v out2 - the output of the linear controller managed by fb2 and gate2 v out3 - the output of the linear controller managed by fb3 and gate3 these refer to the typical application circuit s on page s 3 and 14 . re v . 2.01 6/26/2003
www.siliconstandard.com 13 of 14 ss6341 n applicatio n circuit + + ugate phase vin 2 lgate gate3 pgnd fb3 gate2 fb2 comp1 ss gnd +5vin vcc +12vin 15 ocset 4 7 11 8 6 2.5v out 3.3v out + 5.0 vin 12 13 16 1 2 14 14 5v out + 5 gnd fb1 3 sd 10 + + 5.0v in 1000 m f *5 0.1 m f 1000 m f*2 2k 24k 8.2k 91k 1000pf 33pf 3.9k 2.4k 2.4k 2.4k 1 m h 7 m h 1000pf k 10 0.1 m f 1 m f ss6341cs typical application circuit for multiple ou t puts re v . 2.01 6/26/2003
www.siliconstandard.com 14 of 14 ss6341 n package dimensions l 16 lead plastic so ( 300 mil) (unit : mm) symbol min max a 2.35 2.65 a1 0.10 0.30 b 0.33 0.51 c 0.23 0.32 d 10 .10 10.50 e 7.40 7.60 e 1.27(typ) h 10.00 10.65 h e e b c a a1 d l l 0.40 1.27 information furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by i mplication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. re v . 2.01 6/26/2003

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